1. Field of the Invention
The present invention generally relates to calibration grids usable in electron beam lithography apparatus and, more particularly, to a structure and method of fabrication for reusable, planarized calibration grids which are relatively insusceptible to damage and easily cleanable which results in increased manufacturing yields.
2. Description of the Prior Art
In processes for the fabrication of semiconductor and other devices, it is common to achieve patterning of a layer by covering the layer with a resist, sensitizing the resist in selected areas so that exposure to a chemical agent will cause a reaction resulting in the removal of the resist material from either selected or non-selected areas of the layer. Thereafter, further layers can be deposited or portions of the layer removed by additional processes such as chemical or plasma etching, sputtering, vapor deposition and the like. These processes may be performed numerous times in the fabrication of complex semiconductor integrated circuits.
The step of sensitizing of areas of the resist can be done in many ways and numerous resists have been developed to be sensitized by exposure to different sensitizing agents such as light, ultra-violet radiation, electron beams, X-rays, etc. Since the resolution of the patterning of the resist layer is limited by the wavelength of radiation used to sensitize the layer, optical patterning has given way to electron beam lithography as the size of elements in the integrated circuit has diminished and the degree of integration has increased. A discussion of electron beam lithography, resists and related matters can be found in "VLSI Handbook", Norman G. Einspruch, editor, Published by Academic Press, Inc., Orlando, Fla., 1985, particularly at pages 328-380.
While electron beam lithography can be used for directly patterning resists used in the formation of a chip, it is much more often employed in the fabrication of masks which are subsequently used for optical, ultra-violet or x-ray sensitization of the resists during fabrication of chips. The reason for this is that electron beam lithography is necessarily serial in nature and the throughput using mask exposures is much higher. However, in densely integrated circuits, the formation of masks requires a stepping camera to replicate the elemental patterns at numerous locations which is a multi-step process which must also be performed serially. In comparison with other serial processes, electron beam lithography is extremely fast and requires only a single step to pattern a portion of the resist for a mask. Therefore, the throughput for mask formation with electron beam lithography is several orders of magnitude greater than with optical techniques. The resolution of such masks produced by electron beam lithography is also fully compatible with X-ray lithography for manufacture of the chips.
As with any lithographic process, alignment and calibration are critical for producing articles, such as chips or masks, with high geometric accuracy. Electron beam lithography, being a serial process, potentially allows such alignment and calibration to be done often during the sensitization process. In electron beam lithography, calibration is done with the aid of a calibration grid. Typically, the beam will be swept to locate a grid position and then deflected by a precise distance from such a datum point to a point where impingement of the beam is desired. High accuracy may be enhanced through the use of correction look-up tables, error measurement and smoothing and various interpolation techniques such as spline-fitting to reduce positioning errors to the order of 30 ppm. These techniques are discussed in more detail in "Correction of Nonlinear Deflection Distortion in a Direct Exposure Electron-Beam System" by H. Engelke et al., IBM J. Res. Develop., November, 1977. However, all of these techniques rely on the accuracy of the sensing of beam position by means of a calibration grid placed in the exposure field of the beam and, therefore, the grid and the accuracy thereof is critical to the electron beam lithographic process.
A calibration grid as known in the prior art is formed by an array of orthogonal lines of gold on a substrate or body which is typically of silicon or similar semiconductor material. The array of gold lines intersect to form approximately one thousand square holes in the gold layer, each square measuring, typically, 25 .mu.m on a side and at a typical spacing, on centers, of 37.5 .mu.m. Measurement of beam position is accomplished by detecting changes of backscatter of electrons as the beam is swept across the calibration grid. Backscatter occurs more strongly when the beam impinges on the more dense gold than on the relatively less conductive surface on which the grid is formed. By scanning the calibration grid and noting the times of change of backscatter, deviation from ideal times and ideally linear sweeps can be discovered and corrections developed. Nevertheless, many sweeps per hole of the calibration grid are necessary to allow compensation for the edge roughness of the gold lines forming the grid which is a significant source of positioning error. Further, while the gold lines are relatively thin, the surface of the gold layer is not coplanar with the surface of the grid, causing a certain degree of parallax error and an additional component of the problem of edge roughness.
While extremely high accuracy can be achieved by this arrangement, several problems have been encountered. The grid, itself, must be fabricated by a technique very similar to that employed to form integrated circuits and masks. Although calibration grids are of relatively simple structure, the size of approximately one inch, square, the number and length of lines and the extremely low fault tolerance for the intended use combine to significantly reduce manufacturing yields and raise costs. Consider, for instance, that redundant structures can be fabricated on integrated circuit chips but not on calibration grids and that any width variation in the gold lines greater than irreducible edge roughness when the lines are formed with the known "lift-off" process will render the grid unusable whereas a line must be broken or be so thin as to cause a substantial resistance to cause a fatal defect in an integrated circuit. Also, since they cannot be encapsulated, mechanical damage and contamination also reduce manufacturing yields.
The "lift-off" process by which calibration grids known in the art are typically made includes, as shown in FIG. 1a, the formation of a multi-layer resist including a stand-off layer 11, placed on the grid surface of a substrate 10, an intervening layer 12 placed on the stand-off layer 11 and an imaging layer 13 placed on the intervening layer 12. To improve adhesion of gold to areas of the substrate or body 10, it is common to also include a thin layer of chromium (not shown) between the surface of the substrate, either before applying the resist or at least before deposition of the gold. It is also common to provide a layer of silicon oxide on the surface of substrate 10, indicated by the dotted line in FIG. 1a. After patterning of the imaging layer by selective sensitization, for example, by exposure to light 14, patterns 15 in the imaging layer, shown in FIG. 1b, are etched through the intervening and stand-off layers by ion etching. Then, as shown in FIG. 1c, a gold layer 16 is formed over the entire surface of the grid. When the remaining multi-layer resist is removed from the grid, as shown in FIG. 1d, the overlying areas of gold are also lifted off, leaving only the gold 17 which has reached the grid surface during deposition. This process will also result in some unavoidable degree of edge roughness of the gold lines as indicated at 18 of FIG. 1d. Some thickness variation will also inevitably occur as indicated at 19c of FIG. 1d. While this process is preferable to others known in the art the proportion of defective grids is significant and the yield is relatively low.
Contamination of the grid during use also reduces the useful lifetime of a calibration grid. During the patterning of a resist, material will be outgassed from the resist. Due to the proximity of the grid to the exposed resist, purging of the outgassed material by the evacuation system of the electron beam lithography apparatus cannot be adequately complete to prevent the material from depositing on the grid and particularly the gold lines thereon. When the electron beam again impinges of the grid, the deposited hydrocarbon material is hardened and becomes somewhat conductive, tending to charge to a certain level and then to discharge by conduction. The conductive lumps 19 on the grid lines may significantly change the effective dimensions 19a and locations of the areas 19b in which strong backscattering will occur, yielding unpredictable significant positioning errors of the beam. Also, although the effect is small, height variation 19c in the gold grid lines will produce some parallax error 19d if the beam, indicated by a chain line, is not vertical when it impinges on the calibration grid. This parallax error may fluctuate with the height of the deposited grid line.
More importantly, the effect of charging, even of the grid itself, causes local deflection of the electron beam, causing very significant errors in calibration. Therefore, the grid must be highly conductive. The tendency of the hydrocarbon lumps to charge and discharge causes the local deflection to be time-variable, making extrapolation of exposure location on the surface to be exposed even less reliable. Since this form of contamination can occur during patterning of a resist layer of a mask or integrated circuit, the manufacturing yield of such masks or integrated circuits will also be reduced, increasing the costs attributable to the calibration grid. Once contaminated in this manner, the grid cannot be cleaned or reused since the softness of the gold particularly compared to the hardness of the hydrocarbon material and the exposed location and poor adhesion properties, even with the use of a chromium interlayer structure causes fatal defects to be engendered in the calibration grid by any known cleaning process which might be employed.
From the above, it is seen that while high positioning accuracy can be achieved through the use of a calibration grid, the structure of the grid causes substantial expense which is attributable to the electron beam lithography process.
It was noted above that the resolution of a sensitization process is theoretically limited by the wavelength of the exposure medium such as light, electron beam, x-rays, etc. In practice, the accuracy of exposure positioning imposes a limit on the integration density on the integrated circuit or feature density, as applied to a mask or other device, which may be fabricated by electron beam lithography. For this reason, it is common to utilize semiconductor structures which are tolerant of misregistration and mislocations of areas of particular layers and groups of layers. It is also common practice to impose design rules which do not fully exploit potentially available density of element location to allow for errors of positioning due to the disadvantages of prior calibration grid structures.